-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY Random_Data_tb IS
		generic ( width : integer :=  4 );
  END Random_Data_tb;

  ARCHITECTURE behavior OF Random_Data_tb IS 

  -- Component Declaration
          COMPONENT Random_Data
				generic ( width : integer :=  6 ); 
				Port ( clk : in  STD_LOGIC;
					en : in  STD_LOGIC;
					data_out : out  STD_LOGIC_VECTOR(width-1 downto 0));
          END COMPONENT;

          SIGNAL locClk :  std_logic := '0';
			 signal locEn : std_logic := '0';
          SIGNAL RandData :  std_logic_vector(width-1 downto 0);
          

  BEGIN

  -- Component Instantiation
          Rand1: Random_Data 
			 generic map (width => width)
			 PORT MAP(
                  clk => locClk,
                  en => locEn,
						data_out => RandData
          );
			 
		locEn <= '1';

  --  Test Bench Statements
     tb : PROCESS
     BEGIN
		
        wait for 10 ns; -- wait until global set/reset completes

        locClk <= not locClk;

     END PROCESS tb;
  --  End Test Bench 

  END;
